HSIC USB 2.0 PHY IP
TUSB1210-Q1 data sheet, product information and support | TI.com
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
ULPI - Kcchao
USB 2.0 PHY IP core | Arasan Chip Systems
PhyWhisperer-USB - NewAE Hardware Product Documentation
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
DE10-Advance Hardware Manual revC Chapter5 USB OTG - Terasic Wiki
PhyWhisperer-USB | Crowd Supply
Mixed-Signal Verification for USB 2.0 Physical Layer IP
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
USBPHYC internal peripheral - stm32mpu
The Next-Generation Interconnect | Mouser
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
USB 2.0 Full High Speed Solution | NXP Semiconductors
Canovatech - CT25201_PHY
USB 3.0 PHY for SoC Designs | Cadence IP
Difference between USB and ULPI - Electrical Engineering Stack Exchange
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
PCIe/USB/SATA PHY Appilcation example | Renesas
USB 2.0 Device Controller for SoC Designs | Cadence IP
USB 2.0 PHY for SoC Designs | Cadence IP
USB 2.0 Solutions | Arasan Chip Systems
USB 3.0 PHY IP Core
The USB 2.0 Device IP core | Arasan Chip Systems
